In recent years non-volatile memories have become established in a variety of electronic systems, especially mobile systems. For example, non-volatile memories are widely employed in a variety of electronic products such as portable computers, digital cameras, mobile telephones, and other similar products that are becoming increasingly smaller in size and require increasingly higher memory storage capacity to support advanced applications. To keep pace with these advanced applications, non-volatile memories are being manufactured with higher levels of integration, faster response, higher reliability, lower power consumption, and increased storage capacity.
One way to achieve these ever more demanding requirements is to downscale the non-volatile memory cells. Higher storage capacity for non-volatile memories may be achieved by increasing the memory cell density and reducing the size of cell components such as the floating gate and the control gate, among other elements. Conventional planar semiconductor memory architectures require too much real estate per memory cell and are difficult to downscale to achieve denser cell layouts to effectively increase the memory capacity on a wafer.
Vertically oriented memory cell architectures having a thin vertical Si body and two sided flash cells, however, may be configured to achieve a denser memory cell layout. Although the vertical nature of these memory cell structures provide for denser memory cell layout, these structures lack the necessary overlapping areas between the control gate and the floating gate to yield a suitable gate coupling ratio (GCR). The importance of a suitable GCR is explained below.
Non-volatile memories, such as flash cells, may be fabricated using a metal-oxide-semiconductor (MOS) process. An MOS memory cell array may comprise electrically isolated floating gate structures formed of polycrystalline silicon (polysilicon) surrounded by a silicon dioxide (SiO2) insulative layer. The floating polysilicon gate is electrically isolated from the substrate regions of the semiconductor by the SiO2 insulative layer. Cells of this type also may comprise an n-channel MOS transistor.
The cell operation is controlled by storing electron charge on the electrically isolated floating polysilicon gate. A linear capacitor network is formed of the SiO2 insulative layers surrounding the floating gate and the terminals of the source, drain, transistor channel, and polysilicon control gate. Electrical access to the floating gate is only through this linear capacitor network. The capacitance of the cell may be defined in terms of capacitive coupling ratios, including, for example, the gate coupling ratio (GCR), drain coupling ratio (DCR), and source coupling ratio (SCR). Due to the capacitive coupling, any change in control gate voltage produces a change in floating gate voltage in accordance with the GCR. A suitable GCR for proper memory operation is ˜0.6. This may be referred to as a “golden ratio” for memory cell structures that governs the development of the scaled memory cells, such as, scaled flash memory cells, for example.
Due to the horizontal orientation of the gates in conventional planar flash memory cells, for example, a suitable gate coupling ratio of ˜0.6 may be achieved by extending the floating gate and the control gate laterally (e.g., horizontally) into the isolation area to increase the overlapping portions of the gates. The amount of overlapping determines the capacitance coupling between the gates and thus the overlapping regions may be adjusted to yield a suitable or desirable GCR. Vertical flash cell structures, however, do not have an equivalent isolation area available to extend the gates, and thus, increasing or tuning the GCR in a vertical memory structure is not as trivial as in the planar structures. Accordingly, conventional vertical memory structures have a GCR of ˜0.33, which is substantially below the desired golden ratio.